A DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) is an SDRAM having a high-speed data transfer function capable of performing data reading and writing at both times of a rise and a fall of a clock signal (pulse) for achieving synchronization between circuits. The DDR SDRAM uses a data strobe (DQA) signal in order to inform a timing of performing data input/output with a frequency twice as fast as an external clock signal. The data strobe signal DQS is a bi-directional strobe signal, and functions as a data input/output operation reference clock at the time of a read/write operation. In the read operation, an edge of the data strobe signal DQS coincides with an edge of read data. Accordingly, when the read data is received from the DDR SDRAM, the received data strobe signal DQS is internally delayed up to the middle of the read data.
Now, assume that a read command (READ) is received in an active state the DDR SDRAM, whereupon the data strobe signal DQS changes from a high-impedance (intermediate level) to a low level. A period of this low level is a preamble which will become a preparatory period for a data latch timing. The preamble is generated approximately one clock before initial data is output. Following the preamble, the data strobe signal DQS toggles (alternates) at the same frequency as the clock signal during a period in which an effective data signal is present at a data input/output terminal (DQ). A low-level period after a last data has been transferred is a postamble. The postamble is generated during a period of approximately a half clock from an edge of the last data signal.
Accompanying increase in functions and trend of higher functionality of mobile devices in recent years, increase in the capacity and downsizing of a DDR DRAM mounted on the mobile devices are demanded. For this reason, it is necessary to further reduce the mounting area of the DDR, and reduction in the package size of the DDR DRAM is also demanded. Further, by MCP (multi chip packaging) in which two or more DDR DRAMs of the same capacity are mounted within a same package, a semiconductor device with a large capacity and a reduced mounting area is implemented. In such a semiconductor device, a plurality of DDR DRAMs are connected in parallel, accompanied by common connection of a lot of input/output signal lines.
Patent Document 1, for example, describes a semiconductor device into which a plurality of semiconductor chips each including an input/output synchronization signal terminal or an output synchronization signal terminal are incorporated. In this semiconductor device, an optional function (such as a bonding option chip, a fuse option, or the like) that brings an output of a DQS output circuit always into a high impedance state is incorporated into the DQS output circuit on a discrete chip. When DQS terminals of a plurality of semiconductor chips are connected in common, this function causes only one of the chips connected in common to output the DQS signal in a normal state and causes remaining DQS terminals to be in the high-impedance state. With this arrangement, a through current is prevented from flowing across a power supply and the ground via the DQS terminals.
Further, when the DDR DRAM is used, a higher read speed, for example, is demanded. For this reason, various proposals have been made so as to eliminate an undesired operation as much as possible. Patent Document 2, for example, discloses a memory interface control circuit capable of improving immunity of read data to glitch noise when the read data is transferred between a memory (DDR-SDRAM, or a DDR2-SDRAM, in particular) and a memory controller LSI, and alleviating a constraint on a physical arrangement relationship between the memory and the memory controller LSI.
[Patent Document 1] JP Patent Kokai Publication No. JP-P2006-24663A
[Patent Document 2] JP Patent Kokai Publication No. JP-P2006-260322A